|Tags||hardware utilities c linux system-administrators|
2022081213 Aug 2022 04:40 major feature: Corrected (synth) decoding for (0,6),(8,6) Intel Snow Ridge/Parker Ridge. Added 8000000a/edx X2AVIC flag, from Linux kernel patches. Improved (synth) decoding for (0,6),(9,7),2, adding Added Alder Lake-HX. Reverted May 27 2022 split of 7/0/ebx hack to report bit 22 as RDPID on AMD architectures. Generalized (0,6),(8,14),9,YP stepping case to include Pentium 4425Y, from instlatx64 sample. Updated 7/0/edx comments to reflect original info source for SRBDS mitigation MSR available, previously just marked LX*. Updated 7/0/edx comments to reflect original info source for RTM transaction always aborts, previously just marked LX*. Added (vuln to branch type confusion synth) synthetic leaf to correct for the one known inaccuracy. Added those two original source web pages from Intel: Intel Transactional Synchronization Extensions (Intel TSX) Memory and Performance Monitoring Update for Intel Processors (Article ID 000059422), Special Register Buffer Data Sampling. Added 0x80000008/ebx not vulnerable to branch type confusion flag from "Technical Guidance For Mitigating Branch Type Confusion (White Paper)". Also added a synthetic flag to correct the special case for Family 0x19, where the raw flag is documented to be wrong. Added 7/2/edx indirect branch prediction related flags from Intel's "Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598". Added (uarch synth) decoding for (0,6),(6,14) Cougar Mountain, mentioned as Airmont by Intel's "Retpoline: A Branch Target Injection Mitigation". Added "Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598" and "Retpoline: A Branch Target Injection Mitigation". Clarified (synth) for (0,6),(8,13) Tiger Lake-H from SSG*. Added support for hypervisor+3/ecx (Microsoft) flags. Added support for hypervisor+0xa/eax (Microsoft) VMCS GuestIa32DebugCtl support flag. Added support for hypervisor+0xa/ebx (Microsoft) VMCS HvFlushGu
2022022425 Feb 2022 20:03 major feature: Added (synth) and (uarch synth) decoding for AMD Rembrandt E1. Added hypervisor+4/eax (Xen) expanded destination id bit. Removed bogus 7/1/eax bit 24 "AMX tile support". Renamed 6/eax bit to 23 to mention Thread Director. Widened 6/ecx number of enh hardware feedback classes from bits 8-11 to bits 8-15. Renamed 7/1/eax bit to 10 to include "fast". Added 7/1/ebx decoding. Added 0x14/0/ebx decoding for support for IA32_RTIT_CTL EventEn DisTNT bits. Added synth decoding for (0,6),(11,15) Alder Lake, based on MSR_CPUID_table*. Confirmed synth decoding for (0,6),(10,8) Rocket Lake. Added (synth) steppings based on instlatx64 samples. Corrected missing Core name for (0,6),(9,7) Alder Lake-S A0 stepping. In 0x18 leaves, line up values better.
2021121011 Dec 2021 09:28 major feature: Added new fields for AMD family 17h model 01h B1, including SME/SEV. Added new fields for Intel CET. Added many new fields in Microsoft hypervisor leaves.
2018051919 May 2018 13:30 major feature: Added new fields for AMD family 17h model 01h B1, including SME/SEV. Added new fields for Intel CET. Added many new fields in Microsoft hypervisor leaves.
2018041920 Apr 2018 06:48 major feature: Added synth decoding for Pentium Silver, Xeon Scalable, Bay Trail, and AMD Zen. Added leaf 18 (deterministic address translation), many new bit fields bugfixes.
2017041919 Apr 2018 15:29 major feature: Added synth decoding for Pentium Silver, Xeon Scalable, Bay Trail, and AMD Zen. Added leaf 18 (deterministic address translation), many new bit fields bugfixes.
2017012222 Jan 2017 21:06 major bugfix: Added proper synth decoding for AMD Steamroller, Jaguar, Puma, and Excavator; Intel Kaby Lake and Quark; and fixed some bugs and omissions with other processor families. Supports building as PIC/PIE.
2016120101 Dec 2016 14:25 major bugfix: Fixed a bug that resulted in omission of some AMD cache information (0x8000001d subleaves), and Xen hypervisor information (0x40000003 subleaves).
2016111414 Nov 2016 13:54 major feature: Added early synth decoding for Kaby Lake, Apollo Lake, and Knights Mill, and updated synth decoding for few others. Added decoding for new AVX512 feature flags and CLWB. Added decoding for L3 cache QoS monitoring, total local bandwidth monitoring, and nominal core crystal clock. Added -l/--leaf and -s/--subleaf options for dumps of not-yet-supported leaves. Fixed bug in determining correct 0x8 subleaves to display.
2016081415 Aug 2016 04:10 major feature: Updated synth decoding for Knights Landing, Broadwell, and several Atom processors. Added decoding for 0x12 and 0x17 leaves, and improved decoding for 7, 0xd, 0x10, and 0x14 leaves. Added cpuinfo2cpuid script to ease use of cpuid when only archived /proc/cpuinfo information is available.
2015101717 Oct 2015 20:20 major feature: Updated synth decoding for Knights Landing, Broadwell, Skylake, Ivy Bridge-EX, Merrifield, Moorefield, and SoFIA. Added new leaf decodings for 0xd and 0x14. Added new cache descriptors for leaf 0x2.
2015060607 Jun 2015 01:03 major feature: Support for several leaf updates, including information on XSAVEC, XGETBV, and XSAVES/XRSTORS instructions. Decoding for more Haswell processors, Broadwell, Cherry Trail, and Avoton. And bugfixes.
Submitted byTodd Allen
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