|Tags||hardware utilities c linux system-administrators|
2018041920 Apr 2018 06:48 major feature: Added synth decoding for Pentium Silver, Xeon Scalable, Bay Trail, and AMD Zen. Added leaf 18 (deterministic address translation), many new bit fields bugfixes.
2017041919 Apr 2018 15:29 major feature: Added synth decoding for Pentium Silver, Xeon Scalable, Bay Trail, and AMD Zen. Added leaf 18 (deterministic address translation), many new bit fields bugfixes.
2017012222 Jan 2017 21:06 major bugfix: Added proper synth decoding for AMD Steamroller, Jaguar, Puma, and Excavator; Intel Kaby Lake and Quark; and fixed some bugs and omissions with other processor families. Supports building as PIC/PIE.
2016120101 Dec 2016 14:25 major bugfix: Fixed a bug that resulted in omission of some AMD cache information (0x8000001d subleaves), and Xen hypervisor information (0x40000003 subleaves).
2016111414 Nov 2016 13:54 major feature: Added early synth decoding for Kaby Lake, Apollo Lake, and Knights Mill, and updated synth decoding for few others. Added decoding for new AVX512 feature flags and CLWB. Added decoding for L3 cache QoS monitoring, total local bandwidth monitoring, and nominal core crystal clock. Added -l/--leaf and -s/--subleaf options for dumps of not-yet-supported leaves. Fixed bug in determining correct 0x8 subleaves to display.
2016081415 Aug 2016 04:10 major feature: Updated synth decoding for Knights Landing, Broadwell, and several Atom processors. Added decoding for 0x12 and 0x17 leaves, and improved decoding for 7, 0xd, 0x10, and 0x14 leaves. Added cpuinfo2cpuid script to ease use of cpuid when only archived /proc/cpuinfo information is available.
2015101717 Oct 2015 20:20 major feature: Updated synth decoding for Knights Landing, Broadwell, Skylake, Ivy Bridge-EX, Merrifield, Moorefield, and SoFIA. Added new leaf decodings for 0xd and 0x14. Added new cache descriptors for leaf 0x2.
2015060607 Jun 2015 01:03 major feature: Support for several leaf updates, including information on XSAVEC, XGETBV, and XSAVES/XRSTORS instructions. Decoding for more Haswell processors, Broadwell, Cherry Trail, and Avoton. And bugfixes.
Submitted byTodd Allen
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